Zadc is an 8 channel gate generator, that converts an analog signal (a control voltage) into an 8-bit number, where each bit is represented as a gate output. Outputs gates can be 100% duty cycle (legato/latch) or momentary triggers, with the duration being user settable.
Video Manual: https://www.youtube.com/watch?v=B4hhqP6GU1Y
In - The current value of the CV source will be converted into an 8-bit number when the gate (input #2) goes high. This jack expects -5v to 5v.
Clock - When a leading edge is detected, the value at IN will be sampled and applied to the output gates. This jack is effectively the sampling rate of the digital conversion.
1-8: When the input gate is high, the value at IN will be converted into an 8-bit number. Each bit which is high, will then cause the corresponding gate to be high as well.
Latch / Trigger switch - When set to the left ("latch") this will cause output gates to remain high until the next pulse is received at the gate input (input #2). If the subsequent gate is high, the output port will remain high. When set to the right ("trigger") this will cause the output gates to fire out a momentary trigger. The duration of the trigger can be set with the trigger duration knob (below).
Trigger duration knob - When in trigger mode, sets the duration of the output trigger. Range is 1ms to 50ms.
Performance toggle switch 1-8: Each gate has a 3-position toggle switch. To the far left the gate behaves as normal, in the middle the gate is always low (muted), and to the far right the gate is inverted. Toggle switch state is evaluated on the next input gate pulse (input #2) to avoid triggering output gates out of time.
Example #1: An input value of 5v will be converted to 255(d) or 11111111(b). This will cause all output gates to be set high.
Example #2: An input value of 0v will be converted to 128(d) or 10000000(b). This will cause all but the 8th gate to be set low, with the 8th gate being set high.
Example #3: An input value of -1v will be converted to 102(d) or 01100110(b). This will cause the first gate to be low, the 2nd and 3rd gates to be high, the 4th and 5th gates to be low, and the 6th and 7th gates to be high, and finally the 8th gate to be low.
Example #4: An input value of -5v will be converted to 0(d) or 00000000(b). This will cause all output gates to be set low.
Feb 12, 2021
- LEDs now stay lit for slightly longer when using very short trigger durations
- Digit counter now clears when disconnecting input or clock jack
Feb 10, 2021
- Initial release