The ACE Delay Line has 8 cascaded analogue shift registers which delay the input signal for 1 to 8 sample periods. The Delay Line has two main functions within the ACE environment:
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Each module in Voltage Modular requires at least one sample period before a signal at the input gets processed and then presented to the output. The Delay Line allows the programmer to ensure that values propagate through different processing paths with the same time delay, so that they can be operated on simultaneously when they ‘join up’ again.
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It allows the programmer to have a series of events take place in a specific order, such as injecting initial conditions into Integrators, placing them into the Run state, and triggering state changes on SR-Latches.